Semiconductors supply chain map: who makes each part, and where
A chip starts as a polished silicon wafer, is patterned layer by layer in a fab with photomasks, gases and chemicals, then cut, mounted on a substrate, wired, molded and tested. Behind the fab stand the tool makers that equip it.
CHIPS Act guardrails and export controls attach to specific companies and countries along that chain. A buyer or an award recipient has to know not only the fab but its suppliers and its tools.
The Verdex semiconductor map shows the companies at every step of this chain, where their plants are, and how each stands under the rules that apply to the sector. Each step below opens its own page: what happens at that step, who does it, and where. How a chip is made, step by step.
Raw Extraction
- Quartz & Silica Mining: High-purity quartz is extracted from deposits. Feeds the silicon chain and fused-quartz consumables (crucibles).
Silicon Refining
- Metallurgical Silicon: Quartz is reduced with carbon in submerged arc furnaces to metallurgical-grade silicon (~98-99% purity).
- Electronic-Grade Polysilicon: MG-Si is converted to trichlorosilane, distilled, and redeposited at 9N-11N purity (Siemens process). A distinct industry from solar-grade polysilicon: Hemlock (US), Wacker (DE), Tokuyama (JP), Mitsubishi Materials (JP), REC (US/NO), OCI (KR/MY).
Wafer
- Quartz Crucibles: High-purity quartz fused into crucibles consumed in ingot growth.
- Silicon Wafer (Ingot to Polished/Epi): Polysilicon is melted and pulled into a single-crystal ingot, sliced, and polished to atomic flatness; optional epitaxial layer. No separate merchant ingot industry exists.
Fab Materials
- EUV Mask Blanks: Ultra-flat low-thermal-expansion substrates with multilayer reflective coatings, the blank a photomask is written on. Hoya + AGC (both JP) ~93% duopoly — a single-country chokepoint.
- Photomasks: Patterned masks (reticles) that project each circuit layer onto the wafer. Merchant: Photronics (US), Toppan/Tekscend (JP), DNP (JP); ~63% of mask value is captive shops inside Intel/TSMC/Samsung.
- Photoresists: Light-sensitive polymers coated on the wafer for each lithography pass. JSR, Tokyo Ohka, Shin-Etsu Chemical, Sumitomo Chemical, Fujifilm EM (all JP), Dongjin (KR). Japan ~70%+ overall, ~100% of EUV-grade.
- Electronic & Specialty Gases: High-purity process gases (silane, NF3, WF6, neon for excimer lasers, etc.) consumed per wafer pass. Linde (UK/US), Air Liquide (FR), Air Products (US), Nippon Sanso (JP), Messer (DE); top 5 ~80%. Neon purification historically Ukraine/Russia.
- High-Purity Wet Chemicals: Ultra-pure acids and solvents for etch and clean steps. Ultra-pure HF: Stella Chemifa + Morita (JP, near-exclusive); Kanto (JP), Entegris (US), BASF (DE).
- CMP Slurries & Pads: Chemical-mechanical planarization consumables, used up per wafer. Slurry: Entegris (US) ~40%, Fujimi (JP), Resonac (JP); pads: DuPont (US) >50%.
Wafer Fabrication
- Wafer Fabrication: Hundreds of process steps (deposition, lithography, etch, implant, CMP, clean, with metrology throughout) build the circuits on the wafer; ~3 months per wafer.
Packaging Materials
- Packaging Substrates (ABF/FC-BGA): Organic build-up substrates that carry the die and fan out its connections. Ibiden (JP), Shinko (JP), Unimicron (TW), Nan Ya PCB (TW), AT&S (AT), Samsung E-M (KR); top 5 ~74%.
- ABF Film: Ajinomoto Build-up Film, the insulating layer laminated into high-end substrates. Ajinomoto (JP) is the sole supplier — the sector's quietest single point of failure.
- Leadframes & Bonding Wire: Stamped/etched metal leadframes and fine gold/copper/silver bonding wire for wire-bonded packages. Wire: Heraeus (DE), Tanaka (JP), Sumitomo MM (JP), MK Electron (KR); leadframes: Mitsui High-tec (JP), Shinko (JP).
- Mold Compounds & Underfill: Epoxy mold compounds that encapsulate the die and underfill materials for flip-chip joints.
Assembly, Packaging & Test
- Assembly, Packaging & Test: Wafers are probed, thinned, and diced; die attached to substrate or leadframe (wire-bond, flip-chip, or 2.5D/3D); encapsulated; final test. The step that hands over a finished, tested chip. Distinct industry: OSATs — ASE (TW), Amkor (US), JCET (CN), Tongfu (CN), Powertech (TW) — plus captive back-end at IDMs and foundries. >=81% of capacity in Asia.
Equipment
- Lithography Tools: Scanners and steppers that project mask patterns onto wafers. ASML (NL) — 100% of EUV; Nikon and Canon (JP) for DUV.
- Deposition, Etch & Implant Tools: Deposition (CVD/ALD/PVD), plasma etch, and ion-implant systems. Applied Materials (US), Lam Research (US), Tokyo Electron (JP), ASM International (NL), Kokusai (JP), Axcelis (US).
- Metrology & Inspection: Defect inspection and measurement systems used throughout the fab. KLA (US) ~55-63%, Hitachi High-Tech (JP), Onto Innovation (US), Nova (IL).
- Wafer Cleaning Tools: Single-wafer and batch cleaning systems between process steps.
- Assembly & Test Equipment: Die/wire bonders, molding systems, and automated test equipment for the back end. ASMPT (HK/SG), Besi (NL), Kulicke & Soffa (SG/US); test: Advantest (JP), Teradyne (US).