Sectors · Chips
How a chip is made
A chip starts as a polished silicon wafer, is patterned layer by layer in a fab with photomasks, gases and chemicals, then cut, mounted on a substrate, wired, molded and tested. Behind the fab stand the tool makers that equip it.
CHIPS Act guardrails and export controls attach to specific companies and countries along that chain. A buyer or an award recipient has to know not only the fab but its suppliers and its tools.
Open the chip mapThe parts, opened up
Drag to turn · click a part
- 1WaferThe polished silicon disc the chips are built on.10 makers
- 2DieThe patterned, fabricated circuit, cut from the wafer.79 makers
- 3SubstrateThe laminate the die is mounted on inside the package.18 makers
- 4Leadframe and wireThe metal frame and bonding wire that connect the die outward.16 makers
- 5Mold compoundThe epoxy that encases the die.15 makers
- 6Packaged chipThe die packaged and tested.51 makers
The whole chain, step by step
Ends inAssembly, Packaging & Test
Raw material: the trail reaches the ground Not traced yet: there is more upstream
Raw Extraction
Quartz & Silica Mining
raw materialHigh-purity quartz is extracted from deposits. Feeds the silicon chain and fused-quartz consumables (crucibles).
Silicon Refining
Metallurgical Silicon
Quartz is reduced with carbon in submerged arc furnaces to metallurgical-grade silicon (~98-99% purity).
Electronic-Grade Polysilicon
MG-Si is converted to trichlorosilane, distilled, and redeposited at 9N-11N purity (Siemens process). A distinct industry from solar-grade polysilicon: Hemlock (US), Wacker (DE), Tokuyama (JP), Mitsubishi Materials (JP), REC (US/NO), OCI (KR/MY).
Wafer
Quartz Crucibles
High-purity quartz fused into crucibles consumed in ingot growth.
Silicon Wafer (Ingot to Polished/Epi)
Polysilicon is melted and pulled into a single-crystal ingot, sliced, and polished to atomic flatness; optional epitaxial layer. No separate merchant ingot industry exists.
Fab Materials
EUV Mask Blanks
not traced yetUltra-flat low-thermal-expansion substrates with multilayer reflective coatings, the blank a photomask is written on. Hoya + AGC (both JP) ~93% duopoly — a single-country chokepoint.
Photomasks
Patterned masks (reticles) that project each circuit layer onto the wafer. Merchant: Photronics (US), Toppan/Tekscend (JP), DNP (JP); ~63% of mask value is captive shops inside Intel/TSMC/Samsung.
Photoresists
not traced yetLight-sensitive polymers coated on the wafer for each lithography pass. JSR, Tokyo Ohka, Shin-Etsu Chemical, Sumitomo Chemical, Fujifilm EM (all JP), Dongjin (KR). Japan ~70%+ overall, ~100% of EUV-grade.
Electronic & Specialty Gases
not traced yetHigh-purity process gases (silane, NF3, WF6, neon for excimer lasers, etc.) consumed per wafer pass. Linde (UK/US), Air Liquide (FR), Air Products (US), Nippon Sanso (JP), Messer (DE); top 5 ~80%. Neon purification historically Ukraine/Russia.
High-Purity Wet Chemicals
not traced yetUltra-pure acids and solvents for etch and clean steps. Ultra-pure HF: Stella Chemifa + Morita (JP, near-exclusive); Kanto (JP), Entegris (US), BASF (DE).
CMP Slurries & Pads
not traced yetChemical-mechanical planarization consumables, used up per wafer. Slurry: Entegris (US) ~40%, Fujimi (JP), Resonac (JP); pads: DuPont (US) >50%.
Wafer Fabrication
Wafer Fabrication
Hundreds of process steps (deposition, lithography, etch, implant, CMP, clean, with metrology throughout) build the circuits on the wafer; ~3 months per wafer.
Packaging Materials
Packaging Substrates (ABF/FC-BGA)
Organic build-up substrates that carry the die and fan out its connections. Ibiden (JP), Shinko (JP), Unimicron (TW), Nan Ya PCB (TW), AT&S (AT), Samsung E-M (KR); top 5 ~74%.
ABF Film
not traced yetAjinomoto Build-up Film, the insulating layer laminated into high-end substrates. Ajinomoto (JP) is the sole supplier — the sector's quietest single point of failure.
Leadframes & Bonding Wire
not traced yetStamped/etched metal leadframes and fine gold/copper/silver bonding wire for wire-bonded packages. Wire: Heraeus (DE), Tanaka (JP), Sumitomo MM (JP), MK Electron (KR); leadframes: Mitsui High-tec (JP), Shinko (JP).
Mold Compounds & Underfill
not traced yetEpoxy mold compounds that encapsulate the die and underfill materials for flip-chip joints.
Assembly, Packaging & Test
Assembly, Packaging & Test
Wafers are probed, thinned, and diced; die attached to substrate or leadframe (wire-bond, flip-chip, or 2.5D/3D); encapsulated; final test. The step that hands over a finished, tested chip. Distinct industry: OSATs — ASE (TW), Amkor (US), JCET (CN), Tongfu (CN), Powertech (TW) — plus captive back-end at IDMs and foundries. >=81% of capacity in Asia.
Equipment
Lithography Tools
not traced yetScanners and steppers that project mask patterns onto wafers. ASML (NL) — 100% of EUV; Nikon and Canon (JP) for DUV.
Deposition, Etch & Implant Tools
not traced yetDeposition (CVD/ALD/PVD), plasma etch, and ion-implant systems. Applied Materials (US), Lam Research (US), Tokyo Electron (JP), ASM International (NL), Kokusai (JP), Axcelis (US).
Metrology & Inspection
not traced yetDefect inspection and measurement systems used throughout the fab. KLA (US) ~55-63%, Hitachi High-Tech (JP), Onto Innovation (US), Nova (IL).
Wafer Cleaning Tools
not traced yetSingle-wafer and batch cleaning systems between process steps.
Assembly & Test Equipment
not traced yetDie/wire bonders, molding systems, and automated test equipment for the back end. ASMPT (HK/SG), Besi (NL), Kulicke & Soffa (SG/US); test: Advantest (JP), Teradyne (US).