Semiconductorwho makes each step

High-purity quartz is extracted from deposits. Feeds the silicon chain and fused-quartz consumables (crucibles). Same physical step as solar's quartz mining; kept as a distinct per-map node in V1 (Jul 16 decision Q3).

Quartz is reduced with carbon in submerged arc furnaces to metallurgical-grade silicon (~98-99% purity). Same physical step as solar's MGS smelting; distinct per-map node in V1.

• ›Carbon reductant (metallurgical coke / charcoal / coal) is a required input, held at cutoff in V1 — recorded, not modeled as a node (same treatment as solar).

MG-Si is converted to trichlorosilane, distilled, and redeposited at 9N-11N purity (Siemens process). A distinct industry from solar-grade polysilicon: Hemlock (US), Wacker (DE), Tokuyama (JP), Mitsubishi Materials (JP), REC (US/NO), OCI (KR/MY).

High-purity quartz fused into crucibles consumed in ingot growth (countable runs per crucible — passes the decomposition test, like solar's crucibles). Distinct per-map node in V1.

Polysilicon is melted and pulled into a single-crystal ingot, sliced, and polished to atomic flatness; optional epitaxial layer. ONE node for ingot+wafer: the big five do the whole sequence integrated — Shin-Etsu (JP), SUMCO (JP), GlobalWafers (TW), Siltronic (DE), SK Siltron (KR), ~82-90% combined. No separate merchant ingot industry exists. Epi = coefficient profile, not a split.

Ultra-flat low-thermal-expansion substrates with multilayer reflective coatings, the blank a photomask is written on. Hoya + AGC (both JP) ~93% duopoly — a single-country chokepoint, which is why this branch expands one level past photomasks (Jul 16 decision Q5).

Patterned masks (reticles) that project each circuit layer onto the wafer. Merchant: Photronics (US), Toppan/Tekscend (JP), DNP (JP); ~63% of mask value is captive shops inside Intel/TSMC/Samsung.

Light-sensitive polymers coated on the wafer for each lithography pass. JSR, Tokyo Ohka, Shin-Etsu Chemical, Sumitomo Chemical, Fujifilm EM (all JP), Dongjin (KR). Japan ~70%+ overall, ~100% of EUV-grade.

High-purity process gases (silane, NF3, WF6, neon for excimer lasers, etc.) consumed per wafer pass. Linde (UK/US), Air Liquide (FR), Air Products (US), Nippon Sanso (JP), Messer (DE); top 5 ~80%. Neon purification historically Ukraine/Russia.

Ultra-pure acids and solvents for etch and clean steps. Ultra-pure HF: Stella Chemifa + Morita (JP, near-exclusive); Kanto (JP), Entegris (US), BASF (DE).

Chemical-mechanical planarization consumables, used up per wafer. Slurry: Entegris (US) ~40%, Fujimi (JP), Resonac (JP); pads: DuPont (US) >50%.

Hundreds of process steps (deposition, lithography, etch, implant, CMP, clean, with metrology throughout) build the circuits on the wafer; ~3 months per wafer. ONE node deliberately: every process step inside it is done in-house by the fab (TSMC, Samsung, Intel, SMIC, ...). Litho/etch/CMP are not split out — no distinct set of companies performs them as a service; the distinct industries are the suppliers feeding them (the fab-materials branches and the enabled-by equipment).

• ›Logic vs memory share the same input set and differ in amounts — coefficient profiles per D6, not a split (Jul 16 decision Q4 scope: logic/memory silicon only; SiC/GaN is a future sibling map; design/EDA/IP is not a physical production step and is out of scope).
• ›Boundary exclusions (deliberate, recorded): ultrapure water, electricity, commodity copper/steel/aluminum, construction/cleanroom — generic utilities and commodities feed every industry and don't map. Sputter targets recorded as a candidate for later promotion.

Organic build-up substrates that carry the die and fan out its connections. Ibiden (JP), Shinko (JP), Unimicron (TW), Nan Ya PCB (TW), AT&S (AT), Samsung E-M (KR); top 5 ~74%.

Ajinomoto Build-up Film, the insulating layer laminated into high-end substrates. Ajinomoto (JP) is the sole supplier — the sector's quietest single point of failure, which is why this branch expands one level past substrates (Jul 16 decision Q5).

Stamped/etched metal leadframes and fine gold/copper/silver bonding wire for wire-bonded packages. Wire: Heraeus (DE), Tanaka (JP), Sumitomo MM (JP), MK Electron (KR); leadframes: Mitsui High-tec (JP), Shinko (JP). Weakest-sourced branch of the draft; Step 2 company search will firm it up.

Epoxy mold compounds that encapsulate the die and underfill materials for flip-chip joints. Leader set to be firmed up during Step 2 company search.

Wafers are probed, thinned, and diced; die attached to substrate or leadframe (wire-bond, flip-chip, or 2.5D/3D); encapsulated; final test. The step that hands over a finished, tested chip. Distinct industry: OSATs — ASE (TW), Amkor (US), JCET (CN), Tongfu (CN), Powertech (TW) — plus captive back-end at IDMs and foundries. >=81% of capacity in Asia.

Scanners and steppers that project mask patterns onto wafers. ASML (NL) — 100% of EUV; Nikon and Canon (JP) for DUV. Equipment node: attaches to wafer fabrication via enabled-by (ontology Amendment A1), never as an input.

Deposition (CVD/ALD/PVD), plasma etch, and ion-implant systems. Applied Materials (US), Lam Research (US), Tokyo Electron (JP), ASM International (NL), Kokusai (JP), Axcelis (US).

Defect inspection and measurement systems used throughout the fab. KLA (US) ~55-63%, Hitachi High-Tech (JP), Onto Innovation (US), Nova (IL).

Single-wafer and batch cleaning systems between process steps. SCREEN (JP) leads; a distinct specialist population, so its own equipment node under the granularity test.

Die/wire bonders, molding systems, and automated test equipment for the back end. ASMPT (HK/SG), Besi (NL), Kulicke & Soffa (SG/US); test: Advantest (JP), Teradyne (US).